1. Field of the Invention
The present invention relates to a semiconductor memory device and, more particularly, to a semiconductor memory device having a flash write function.
In a random access memory incorporated in a system, all bit contents are reset to "0" or "1", e.g., upon initialization or the like. In general, bits are sequentially designated and preset data is written in each bit to perform a reset operation. In this method, however, an address must be designated for each bit, and a reset time is undesirably long. In particular, this problem is serious in a RAM having a large capacity, and therefore, a flash write system for writing preset data in units of words has been proposed.
2. Description of the Related Art
The following cross references are related to the flash write system:
(i) U.S. Pat. No. 4,680,734, filed on Aug. 5, 1985, published on Jul. 14, 1987; PA0 (ii) U.S. Pat. No. 4,587,629, filed on Dec. 30, 1983, and published on May 6, 1986; PA0 (iii) Japanese Unexamined Patent. Publication No. 63 -106989, filed on Oct. 24, 1986 and published on May 12, 1988.
In a conventional semiconductor memory device having a flash write function, for example, a given word line is designated in response to an external address signal, and preset data is simultaneously written in a plurality of memory bits connected to the given word line. In such a device, as a memory bit count per word in, e.g., a 1-Mbit (=512 cycles x 2048 bits) dynamic RAM is 2048, a reset time is given as 512 cycles, and as a result, the reset time can be shortened.
In such a conventional semiconductor memory device, however, word lines are sequentially selected in response to an external address signal, and therefore, a flash write address generator must be arranged outside the semiconductor memory device, and the external circuit is undesirably complicated.